Thank you! Now I am suspecting that what I am seeing is related to DMA chaining. Here is what I see: I am repeatedly transferring an 8 word buffer by chaining two DMA channels together. At the end of each block the DMA ISR toggles a GPIO so I can observe the timing. The DMA pacer timer divisor is set to 12500, for 125MHz/12500 = 10kHz transfer rate. I am comparing that output to another output generated by a clk_gpout with divisor set to 100000.
I was expecting the two signals to have the same period, because 8 x 12500 = 100000, but in fact the two signals are not stationary relative to each other, which led me to wonder if the pacer clock was asynchronous to clk_sys. BUT, tweaking the timing until the signals are stationary, I find that a clk_gpout divisor of 100005 does the trick. So, new question: Is this expected behavior with DMA chaining, that some timer cycles are lost in the chaining process, so that two 10 kHz DMA transfers chained together will have a net transfer rate of slightly less than 10 kHz? And if so, is there a fix?
I was expecting the two signals to have the same period, because 8 x 12500 = 100000, but in fact the two signals are not stationary relative to each other, which led me to wonder if the pacer clock was asynchronous to clk_sys. BUT, tweaking the timing until the signals are stationary, I find that a clk_gpout divisor of 100005 does the trick. So, new question: Is this expected behavior with DMA chaining, that some timer cycles are lost in the chaining process, so that two 10 kHz DMA transfers chained together will have a net transfer rate of slightly less than 10 kHz? And if so, is there a fix?
Statistics: Posted by timchinowsky — Thu Jul 04, 2024 1:10 pm