Please does it mean there is no way to output a MCLK frequency at reasonable FS multiple for standard DACs/ADCs which do not have built-in MCLK PLL and require the MCLK (typically between 12Mhz - 50MHz)?...will get you the ability to use clocks derived directly from pll_audio, but only on I2S SCLK pins.
The audio clock tree captured at 48kHz I2S playback shows no such MCLK clk:
Code:
pll_audio_core 4 4 0 801791999 0 0 50000 Y deviceless no_connection_id pll_audio_tern 1 1 0 42199579 0 0 50000 Y deviceless no_connection_id pll_audio_sec 1 1 0 100224000 0 0 50000 Y deviceless no_connection_id pll_audio 2 2 0 267264000 0 0 50000 Y deviceless no_connection_id clk_i2s 2 1 0 3072000 0 0 50000 Y 1f000a0000.i2s i2sclk deviceless no_connection_id pll_audio_pri_ph 0 0 0 133632000 0 0 50000 Y deviceless no_connection_id Code:
pll_audio_core 4 4 0 801561600 0 0 50000 Y deviceless no_connection_id pll_audio_tern 1 1 0 42187453 0 0 50000 Y deviceless no_connection_id pll_audio_sec 1 1 0 100195200 0 0 50000 Y deviceless no_connection_id pll_audio 2 2 0 400780800 0 0 50000 Y deviceless no_connection_id clk_i2s 2 1 0 2822400 0 0 50000 Y 1f000a0000.i2s i2sclk deviceless no_connection_id pll_audio_pri_ph 0 0 0 200390400 0 0 50000 Y deviceless no_connection_id Second question: Please what are the limitations for the pll_audio_core values (i.e. possible non/denom values for the fractional PLL from the 50MHz RP1 xosc)? E.g. 812,851,200Hz would allow generating 45,158,400Hz as well as 22,579,200Hz, the most common MCLK frequencies for the 44.1kHz-family rates.
The 801,800,000Hz for 48kHz seems to use PLL ratio 4009/250 . The 801,561,600Hz for 44.1kHz seems to use 250488 (18bits)/15625 (13bits) which seem quite long-bit values.
Thanks a lot for any info.
Pavel.
Statistics: Posted by phofman — Thu Jul 18, 2024 3:37 pm