Other RP2040 boards • Re: Custom RP2040 | USB Fails to establish communication @ room temp

Removed bad language. Please refrain from using it - this is a forum that is frequented by minors.

Sorry! I tend to use 'industry standard' terminology when posting late at night

The voltage on the clock line is still low, I would be looking at that being shorted to another output. The excessive ringing and step voltage changes are also a symptom of that.

Its pointless doing anything else before diagnosing that voltage, its a clear anomaly.

I don't see a problem running a 133MHz chip at 125MHz, there will be substantial margins in normal usage.

I presume you trimmed the X10 probe? (apologies if that is an insulting question).

I'm not quite sure what you're referring to. At 2V/Div I'm firmly in 3.3Vish territory.
Regarding compensation, that's a good reminder I often forget about that being a thing. That said, I don't believe that to be an issue here. If/when I go back and measure some stuff I'll be sure to re-compensate. The TPP0500 10x probes I used are funky and don't give you the usual screw. It's all handled by my beloved MSO58 <3 love that thing

Note that this is not the default RP2040 behaviour. If your scope shot is really showing the QSPI clock running at 125MHz, then you have a very non-standard configuration.
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So the only way you can get 125MHz on the QSPI clk is if you are heavily overclocking the RP2040 (to 250MHz) and then using the standard /2 divider.

Using such a severe overclock is of course asking for trouble (I would never do so in professional applications), but it still might work if you set PICO_FLASH_SPI_CLKDIV to 4.

Thank you, this is valuable info. I was a bit too hasty to assume the default operation was 125MHz. I guess it's time for me to beat up the owner of the firmware for pushing things so hard. A link to the firmware repo was provided in the original post if you're curious enough. I'll stumble my way through slowing things down.

Given you have sub nano second rise and fall times from the information given I don't think you can say that yet. Have you tried terminating the clock yet ?
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You have made that choice you may not have realised it. The Boot process reads the clock division from the flash ( which you have programmed ) as part of the second stage booting progress. Have a look at chapters 2.7 and 2.8 of the datasheet.

I would definitely like to capture this in a bit more detail to be completely certain. Wanted to check my 'default' behavior before I start futzing with stuff. Have not tried terminating the clock yet, but that should be simple enough, so I'll give it a go when I have an hour to kill.

Thanks for pointing me towards a section of the datasheet, I'll give it a once over. The clock division decision was made by someone else, so I get to go beat them up now >:)

It's fun seeing so many people poke their heads in here. Thanks everyone for the contributions so far.

Statistics: Posted by MMI_Modular — Tue Jul 30, 2024 7:01 pm

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