General • RP2040: Substantial PIO jitter in I2S clock

I'm implementing an I2S output using the PIO code from the pico-examples:
The PIO clock divider is set to an integer value so my BCLK signal should, I understand, have completely consistent timing (in my case, with a period of about 320ns).

Instead I'm seeing occasional but very severe clock jitter - see blue trace below which displays BCLK, triggered on an abnormally short pulse (<130ns low pulse).


The timing error is very specific: occasionally (1 in 10000 or so) following a change in LRCLK, the period drops to about 260ns, then slowly rises over the next ~10 cycles back to the desired 320ns. Duty cycle remains at ~50% throughout.

I'm not seeing any pulses significantly longer than the nominal ~320ns.

Any suggestions as to what might be causing this behaviour? Are there interactions between the two PIO blocks that could be causing this? Or something to do with the clock divider?

Other potentially relevant things:

• The PIO is being fed data through DMA, periodically refreshed through IRQ.
• The problem occurs in software where the RP2040 is fairly busy, running both cores and both PIOs (the other doing SDIO communication with an SD card, using this library https://github.com/carlk3/no-OS-FatFS-S ... -RPi-Pico/).
• I've checked the crystal oscillator and this looks stable.

Statistics: Posted by cgj — Thu Aug 29, 2024 1:26 am

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