I'm designing PCBs around the RP2040 with KiCAD, then ordering them assembled from JLCPCB (minimum order 2). I've had a few wins! However, my second iteration of this one fails to oscillate, and I cannot figure out why.The crystal and crystal circuit are exactly as described in the hardware design guide (ABM8-272-T3 crystal with 15pF load capacitors and a 1k series resistor).
Red: layer 1
Hidden: layers 2 & 3 - ground planes
Blue: layer 4
In all cases, layers 1/2 and 3/4 have dielectric thickness 0.2104mm
PCB 1Both copies of "PCB 1" work correctly. I can probe XIN/XOUT with the oscilloscope (10X) and view a nice sine wave.
PCB 2Both copies of "PCB 2" do not work.
With both copies, I can program through SWD, but the debugger suggests an infinite loop waiting for PLL lock:With both copies, the oscilloscope confirms a fairly dead signal on XIN/XOUT, about 1.6V.
What changed
The differences between PCB 1 and PCB 2:
- moved the crystal left and up, but XIN/XOUT lengths changed only slightly
- switched from 1.6mm PCB to 1mm PCB - layer 2/3 dielectric thickness from 1.1mm to 0.45mm
- routed +1.1V under XIN/XOUT
Questions
Does the layer 2/3 thickness matter here?
The +1.1V line is, of course, driven by the RP2040 internal SMPS. Is it too close to XIN? I assumed it wouldn't be -- there are two ground planes them.
I'm very new to electronics, and this particular component seems very fragile. Is a crystal oscillator any more reliable? (eg ATXAIG-H12-F-12.000MHZ-F25)
- Image may be NSFW.
Clik here to view.
Red: layer 1
Hidden: layers 2 & 3 - ground planes
Blue: layer 4
In all cases, layers 1/2 and 3/4 have dielectric thickness 0.2104mm
PCB 1
- Image may be NSFW.
Clik here to view.
PCB 2
- Image may be NSFW.
Clik here to view.
With both copies, I can program through SWD, but the debugger suggests an infinite loop waiting for PLL lock:
Code:
pll_init (pll=pll@entry=0x40028000, refdiv=refdiv@entry=1, vco_freq=vco_freq@entry=1500000000, post_div1=<optimized out>, post_div2=<optimized out>) at /home/jacobmarble/projects/ia-gear/third-party/pico-sdk/src/rp2_common/hardware_pll/pll.c:6363 while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();What changed
The differences between PCB 1 and PCB 2:
- moved the crystal left and up, but XIN/XOUT lengths changed only slightly
- switched from 1.6mm PCB to 1mm PCB - layer 2/3 dielectric thickness from 1.1mm to 0.45mm
- routed +1.1V under XIN/XOUT
Questions
Does the layer 2/3 thickness matter here?
The +1.1V line is, of course, driven by the RP2040 internal SMPS. Is it too close to XIN? I assumed it wouldn't be -- there are two ground planes them.
I'm very new to electronics, and this particular component seems very fragile. Is a crystal oscillator any more reliable? (eg ATXAIG-H12-F-12.000MHZ-F25)
Statistics: Posted by jacobmarble — Sun Sep 01, 2024 12:42 am
