It doesn't. The OUT instruction always writes 32 bits to the destination, with high-order bits filled with zeros. So in your proposed piece of code, the second OUT will overwrite the results of the first one (the first one might as well have been OUT NULL,15).The second "out ISR, 16" may not do what I'm looking for. It's hard to tell from the data sheet:Code:
out ISR, 16out ISR, 16 ; I can't tell if this one works from the documentationmov X, ISR
This does not make it clear whether the ISR will shift up by countOUT ISR, count sets the input shift counter to count
Only OUT instructions shift the OSR; only IN instructions shift the ISR.
It doesn't. The counter only gets modified for instructions where it tells you so in the datasheet (so for IN, the input counter will be modified but nothing else). Of course the counter only matters if you are using autopull.An alternative is:This will create the correct alignment in the ISR, but the data sheet does not make it clear whether "in OSR, count" modifies the OSR counter.Code:
out ISR, 16in OSR, 16mov X, ISR
So you have the output FIFO configured for 16 bits and you are doing 16-bit writes from the CPU, wanting to reassemble them into 32-bits?Unless I misunderstand, it appears that the fewest cycles for this operation is:Is there a faster way?Code:
out ISR, 16out X, 16in X, 16mov X, ISR
I can't see a faster way to do that (though that doesn't guarantee there isn't one I've missed). But my instinct is that you would be better off keeping the input as 32-bhit: it's much easier to split 32-bit input into 16-bit words (or throw away unwanted halfwords) than to glue the 16-bit values back together.
Statistics: Posted by arg001 — Fri Jan 19, 2024 2:21 pm