No, that's close enough and the QSPI wants to stay on one side if possible. But the caps look big though - are you using 0603 size? I've been using 0402 100nF for years - they take less space and perform much better electrically. Even 1uF are now economical in 0402 (they were premium price until relatively recently).Ok here is a re-draft - just thinking capacitor placement. Will add ground planes and interconnections.
Can get the caps around the pins 48,49 50 closer by routing the QSPI tracks via the back if its worth it?
One trivial improvement: C1's purpose in life is to decouple U1 (the flash). As you've drawn it, the + end of C1 is nicely connected to the power pin on U1, but the GND end is at best going to have a path via the other side. If you rotate C1 so the GND is inside that 3V3 track which passes through there, and push the track going to pin 3 over the top of pin 4, the -ve end of C1 can now connect directly to U1 pin 4 and perform much better. There's then a room for a via hole coupling it to the other side with hopefully a free run on the blue side back to the RP2040 ground pad.
You haven't drawn in your power routing yet - this is always a compromise under the RP2040, as there's room to connect the 1V2 and most of the 3V3 all underneath the chip so both nice and short plus also saving space elsewhere, but you can't quite do all of it. My usual preference is to connect the 1V2 directly under the chip, which then lets you connect two groups of 3V3 pins (top and bottom in the orientation you have) and need to add short jumper on blue side to connect them together. Presumably the 3V3 is going to feed into the CPU zone via the bottom right hand corner (C14 and the other cap next to it and then under the chip).
I'm not sure how many of the GPIO pins you are using, but you won't be able to route them all out with the placement you have now. That bottom edge looks particularly challenging with C5/C14 in the way and the cut-out in the board shape stopping you turning them sideways and/or not letting the tracks escape the area between C5/C14. Maybe the whole lot needs to shift up a bit? But this is quite a tight design on two layers.
Statistics: Posted by arg001 — Fri Jul 05, 2024 12:57 pm