General • Re: RISC-V start of executable, interrupt vectors

Am I correct that one has to use the the 1BS_ENTRY_POINT Meta Block in the image to determine where execution should start and how the stack is initialised ?

Yes. The use of the vector table to provide an entry point and initial SP is a Cortex-M thing.

It seems that Interrupt Vector Tables are in non-fixed locations for Hazard3 code - is there any recommended document describing how interrupts are implemented, configured and used for Hazard3 / RISC-V ? I couldn't identify one.

For standard RISC-V interrupt behaviour, you want datasheet section 3.8.4. For Hazard3's internal interrupt controller (perhaps more relevant here), you want datasheet section 3.8.6.1.

The actual vectoring is implemented in software, with just enough hardware support to make it fast. The section starting at __soft_vector_table in https://github.com/raspberrypi/pico-sdk ... t0_riscv.S roughly corresponds to slots 16 upward in a Cortex-M vector table. The vectoring routine is isr_riscv_machine_external_irq: in that same file.

Statistics: Posted by LukeW — Wed Aug 21, 2024 10:21 pm

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