We have a TPIU with a 4-bit DDR output. As far as I am aware it does not support SWO, based on the css600_tpiu_DEVID definition in the SoC-600M reference manual here: https://developer.arm.com/documentation ... 1/?lang=en
Arm's SoC-600M package doesn't seem to provide components to merge trace output from two cores and output through SWO, so we just have the faster 4-bit output, plus the option of capturing to an on-device buffer using the trace FIFO.
I'll need to check with the engineer who implemented the trace subsystem. I think 3.7.2.9 may just be describing general M33 ETM capabilities, not the specifics of the hardware that was attached to the ETM in this system.
Arm's SoC-600M package doesn't seem to provide components to merge trace output from two cores and output through SWO, so we just have the faster 4-bit output, plus the option of capturing to an on-device buffer using the trace FIFO.
I'll need to check with the engineer who implemented the trace subsystem. I think 3.7.2.9 may just be describing general M33 ETM capabilities, not the specifics of the hardware that was attached to the ETM in this system.
Statistics: Posted by LukeW — Wed Aug 21, 2024 10:25 pm