There are four SRAM domains on RP235x:
Each core could be given a main RAM and scratch pad. Conflicts with Harvard interface are still expected. (Bus priority, stripping and scratch pad should help.) DMA like in the RP2040 will have some level of conflict. (Manage with bus priority.)
You need a high conflict rate for this to make sense. (Higher notions of branch logic will fair much worse.) The CPUs are certainly capable of doing this. XIP provides an instruction L1 cache, but we have limited capacity.
- Stripped Domain 0: 0x20000000 - 0x2003FFFF (256KB) - Main RAM - 4 port
- Stripped Domain 1: 0x20040000 - 0x2007FFFF (256KB) - Main RAM - 4 port
- Non-Stripped Domain 0: 0x20080000 - 0x20080FFF (4KB) - Scratch Pad - 1 port
- Non-Stripped Domain 1: 0x20081000 - 0x20081FFF (4KB) - Scratch Pad - 1 port
Each core could be given a main RAM and scratch pad. Conflicts with Harvard interface are still expected. (Bus priority, stripping and scratch pad should help.) DMA like in the RP2040 will have some level of conflict. (Manage with bus priority.)
You need a high conflict rate for this to make sense. (Higher notions of branch logic will fair much worse.) The CPUs are certainly capable of doing this. XIP provides an instruction L1 cache, but we have limited capacity.
Statistics: Posted by dthacher — Mon Nov 04, 2024 7:32 am