Check the RP2350 datasheet - there is new support in PIO for loading values directly from indexed locations in the FIFOThinking again, the same could be achieved with the ability to turn one FIFO around WITHOUT concatenating it with the other one but using it as a secondary source of data from the processor. Whether there is instruction space to even allow that I haven't checked.Would be useful, though no idea if it is possible without total redesign of the PIO in next gen device. But it would use up a location in the already rather short memory space.
A simpler alternative might be a third scratch register Z sitting in parallel to the FIFO which can only be written to by the main processor and can be loaded into X or Y as needed.
Statistics: Posted by kilograham — Sat Dec 21, 2024 5:54 pm